Add MacOS Section in Installers Branch

MacOS/Examples/4_bit_JK_ff/4_bit_JK_ff-cache.lib

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+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GND-RESCUE-4_bit_JK_ff
+#
+DEF ~GND-RESCUE-4_bit_JK_ff #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND-RESCUE-4_bit_JK_ff" 0 -70 30 H I C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# R-RESCUE-4_bit_JK_ff
+#
+DEF R-RESCUE-4_bit_JK_ff R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "R-RESCUE-4_bit_JK_ff" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_3
+#
+DEF adc_bridge_3 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_3" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -200 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X OUT1 4 550 50 200 L 50 50 1 1 O
+X OUT2 5 550 -50 200 L 50 50 1 1 O
+X OUT3 6 550 -150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_4
+#
+DEF adc_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_jkff
+#
+DEF d_jkff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_jkff" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 600 550 -600 -600 0 1 0 N
+X J 1 -800 400 200 R 50 50 1 1 I
+X K 2 -800 -450 200 R 50 50 1 1 I
+X Clk 3 -800 0 200 R 50 50 1 1 I C
+X Set 4 0 750 200 D 50 50 1 1 I
+X Reset 5 0 -800 200 U 50 50 1 1 I
+X Out 6 800 400 200 L 50 50 1 1 O
+X Nout 7 800 -450 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_4
+#
+DEF dac_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dc-RESCUE-4_bit_JK_ff
+#
+DEF dc-RESCUE-4_bit_JK_ff v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc-RESCUE-4_bit_JK_ff" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library

MacOS/Examples/4_bit_JK_ff/4_bit_JK_ff-rescue.lib

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+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# R-RESCUE-4_bit_JK_ff
+#
+DEF R-RESCUE-4_bit_JK_ff R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "R-RESCUE-4_bit_JK_ff" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library

MacOS/Examples/4_bit_JK_ff/4_bit_JK_ff.cir

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+* /home/fossee/UpdatedExamples/4_bit_JK_ff/4_bit_JK_ff.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Mar  3 18:13:51 2016
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3  Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U2-Pad8_ Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ d_jkff		
+v1  Net-_U1-Pad1_ GND DC		
+v3  Net-_U1-Pad3_ GND DC		
+v4  Net-_U4-Pad2_ GND 0		
+v2  IN GND pulse		
+U5  Net-_U3-Pad7_ Net-_U3-Pad7_ Net-_U1-Pad5_ Net-_U2-Pad7_ Net-_U4-Pad6_ Net-_U5-Pad6_ Net-_U5-Pad7_ d_jkff		
+U7  Net-_U6-Pad3_ Net-_U6-Pad3_ Net-_U1-Pad5_ Net-_U2-Pad6_ Net-_U4-Pad7_ Net-_U7-Pad6_ Net-_U7-Pad7_ d_jkff		
+U10  Net-_U10-Pad1_ Net-_U10-Pad1_ Net-_U1-Pad5_ Net-_U10-Pad4_ Net-_U10-Pad5_ Net-_U10-Pad6_ Net-_U10-Pad7_ d_jkff		
+U6  Net-_U5-Pad7_ Net-_U3-Pad7_ Net-_U6-Pad3_ d_and		
+U8  Net-_U7-Pad7_ Net-_U6-Pad3_ Net-_U10-Pad1_ d_and		
+U4  Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_U4-Pad3_ Net-_U4-Pad4_ Net-_U3-Pad5_ Net-_U4-Pad6_ Net-_U4-Pad7_ Net-_U10-Pad5_ adc_bridge_4		
+v10  Net-_U4-Pad3_ GND 0		
+v11  Net-_U4-Pad4_ GND 0		
+v9  Net-_U4-Pad1_ GND 0		
+v8  Net-_U2-Pad2_ GND 0		
+U2  Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U10-Pad4_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ adc_bridge_4		
+v6  Net-_U2-Pad3_ GND 0		
+v7  Net-_U2-Pad4_ GND 0		
+v5  Net-_U2-Pad1_ GND 0		
+U1  Net-_U1-Pad1_ IN Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ adc_bridge_3		
+U9  Net-_U3-Pad6_ Net-_U5-Pad6_ Net-_U7-Pad6_ Net-_U10-Pad6_ D1 D2 D3 D4 dac_bridge_4		
+R1  D1 GND 1k		
+R2  D2 GND 1k		
+R3  D3 GND 1k		
+R4  D4 GND 1k		
+U11  Net-_U10-Pad7_ GND dac_bridge_1		
+U12  D1 plot_v1		
+U14  D4 plot_v1		
+U15  D3 plot_v1		
+U13  D2 plot_v1		
+
+.end

MacOS/Examples/4_bit_JK_ff/4_bit_JK_ff.cir.out

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+* /home/fossee/updatedexamples/4_bit_jk_ff/4_bit_jk_ff.cir
+
+* u3  net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad5_ net-_u2-pad8_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ d_jkff
+v1 net-_u1-pad1_ gnd  dc 5
+v3 net-_u1-pad3_ gnd  dc 5
+v4  net-_u4-pad2_ gnd 0
+v2  in gnd pulse(0 5 0.1m 0.1m 0.1m 20m 40m)
+* u5  net-_u3-pad7_ net-_u3-pad7_ net-_u1-pad5_ net-_u2-pad7_ net-_u4-pad6_ net-_u5-pad6_ net-_u5-pad7_ d_jkff
+* u7  net-_u6-pad3_ net-_u6-pad3_ net-_u1-pad5_ net-_u2-pad6_ net-_u4-pad7_ net-_u7-pad6_ net-_u7-pad7_ d_jkff
+* u10  net-_u10-pad1_ net-_u10-pad1_ net-_u1-pad5_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ net-_u10-pad7_ d_jkff
+* u6  net-_u5-pad7_ net-_u3-pad7_ net-_u6-pad3_ d_and
+* u8  net-_u7-pad7_ net-_u6-pad3_ net-_u10-pad1_ d_and
+* u4  net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ net-_u4-pad4_ net-_u3-pad5_ net-_u4-pad6_ net-_u4-pad7_ net-_u10-pad5_ adc_bridge_4
+v10  net-_u4-pad3_ gnd 0
+v11  net-_u4-pad4_ gnd 0
+v9  net-_u4-pad1_ gnd 0
+v8  net-_u2-pad2_ gnd 0
+* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u10-pad4_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ adc_bridge_4
+v6  net-_u2-pad3_ gnd 0
+v7  net-_u2-pad4_ gnd 0
+v5  net-_u2-pad1_ gnd 0
+* u1  net-_u1-pad1_ in net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ adc_bridge_3
+* u9  net-_u3-pad6_ net-_u5-pad6_ net-_u7-pad6_ net-_u10-pad6_ d1 d2 d3 d4 dac_bridge_4
+r1  d1 gnd 1k
+r2  d2 gnd 1k
+r3  d3 gnd 1k
+r4  d4 gnd 1k
+* u11  net-_u10-pad7_ gnd dac_bridge_1
+* u12  d1 plot_v1
+* u14  d4 plot_v1
+* u15  d3 plot_v1
+* u13  d2 plot_v1
+a1 net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad5_ net-_u2-pad8_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ u3
+a2 net-_u3-pad7_ net-_u3-pad7_ net-_u1-pad5_ net-_u2-pad7_ net-_u4-pad6_ net-_u5-pad6_ net-_u5-pad7_ u5
+a3 net-_u6-pad3_ net-_u6-pad3_ net-_u1-pad5_ net-_u2-pad6_ net-_u4-pad7_ net-_u7-pad6_ net-_u7-pad7_ u7
+a4 net-_u10-pad1_ net-_u10-pad1_ net-_u1-pad5_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ net-_u10-pad7_ u10
+a5 [net-_u5-pad7_ net-_u3-pad7_ ] net-_u6-pad3_ u6
+a6 [net-_u7-pad7_ net-_u6-pad3_ ] net-_u10-pad1_ u8
+a7 [net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ net-_u4-pad4_ ] [net-_u3-pad5_ net-_u4-pad6_ net-_u4-pad7_ net-_u10-pad5_ ] u4
+a8 [net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ ] [net-_u10-pad4_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ ] u2
+a9 [net-_u1-pad1_ in net-_u1-pad3_ ] [net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ] u1
+a10 [net-_u3-pad6_ net-_u5-pad6_ net-_u7-pad6_ net-_u10-pad6_ ] [d1 d2 d3 d4 ] u9
+a11 [net-_u10-pad7_ ] [gnd ] u11
+* Schematic Name: d_jkff, NgSpice Name: d_jkff
+.model u3 d_jkff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 rise_delay=1.0e-9 jk_load=1.0e-12 fall_delay=1.0e-9 ) 
+* Schematic Name: d_jkff, NgSpice Name: d_jkff
+.model u5 d_jkff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 rise_delay=1.0e-9 jk_load=1.0e-12 fall_delay=1.0e-9 ) 
+* Schematic Name: d_jkff, NgSpice Name: d_jkff
+.model u7 d_jkff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 rise_delay=1.0e-9 jk_load=1.0e-12 fall_delay=1.0e-9 ) 
+* Schematic Name: d_jkff, NgSpice Name: d_jkff
+.model u10 d_jkff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 rise_delay=1.0e-9 jk_load=1.0e-12 fall_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
+.model u4 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
+* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
+.model u2 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
+* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge
+.model u9 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u11 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) 
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(d1)
+plot v(d4)
+plot v(d3)
+plot v(d2)
+.endc
+.end