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[FIRRTL] InferDomains: error when wire is not dominated by domain #10116

@rwy7

Description

@rwy7

When a wire is defined before its associated domains are defined, infer-domains creates a use-before-def.

FIRRTL version 6.0.0
circuit Foo :
  domain ClockDomain :

  extmodule Bar :
    output D: Domain of ClockDomain
    output c: UInt<1> domains [D]
  
  public module Foo :
    wire w : UInt<1>
    inst bar of Bar
    connect w, bar.c
/Users/robertyoung/src/circt/scratch/scratch.fir:10:5: error: operand #0 does not dominate this use
    wire w : UInt<1>
    ^
/Users/robertyoung/src/circt/scratch/scratch.fir:10:5: note: see current operation: %0 = "firrtl.wire"(%1#0) <{annotations = [], name = "w", nameKind = #firrtl<name_kind droppable_name>}> : (!firrtl.domain<@ClockDomain()>) -> !firrtl.uint<1>
/Users/robertyoung/src/circt/scratch/scratch.fir:11:5: note: operand defined here (op in the same block)
    inst bar of Bar
    ^
// -----// IR Dump After InferDomains Failed (firrtl-infer-domains) //----- //
"firrtl.circuit"() <{annotations = [], name = "Foo"}> ({
  "firrtl.domain"() <{fields = [], sym_name = "ClockDomain"}> : () -> ()
  "firrtl.extmodule"() <{annotations = [], convention = #firrtl<convention scalarized>, domainInfo = [[], [0 : ui32]], externalRequirements = [], knownLayers = [], layers = [], parameters = [], portAnnotations = [[], []], portDirections = array<i1: true, true>, portLocations = [loc("/Users/robertyoung/src/circt/scratch/scratch.fir":6:12), loc("/Users/robertyoung/src/circt/scratch/scratch.fir":7:12)], portNames = ["D", "c"], portSymbols = [], portTypes = [!firrtl.domain<@ClockDomain()>, !firrtl.uint<1>], sym_name = "Bar"}> ({
  }) {sym_visibility = "private"} : () -> ()
  "firrtl.module"() <{annotations = [], convention = #firrtl<convention scalarized>, domainInfo = [], layers = [], portAnnotations = [], portDirections = array<i1>, portLocations = [], portNames = [], portSymbols = [], portTypes = [], sym_name = "Foo"}> ({
    %0 = "firrtl.wire"(%1#0) <{annotations = [], name = "w", nameKind = #firrtl<name_kind droppable_name>}> : (!firrtl.domain<@ClockDomain()>) -> !firrtl.uint<1>
    %1:2 = "firrtl.instance"() <{annotations = [], domainInfo = [[], [0 : ui32]], layers = [], moduleName = @Bar, name = "bar", nameKind = #firrtl<name_kind droppable_name>, portAnnotations = [[], []], portDirections = array<i1: true, true>, portNames = ["D", "c"]}> : () -> (!firrtl.domain<@ClockDomain()>, !firrtl.uint<1>)
    "firrtl.matchingconnect"(%0, %1#1) : (!firrtl.uint<1>, !firrtl.uint<1>) -> ()
  }) : () -> ()
}) : () -> ()

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